Intel(r) Tofino(tm) Family, TNA, and P4Studio questions

There is a fair amount of public information about Tofino available, but in general, unless someone can point you at a public source for answers, any specific questions about Tofino hardware features, Tofino Native Architecture (TNA) or features of Intel P4Studio SDE, are best directed to Intel-specific forums created for this purpose, NOT discussed in a public forum.

Here are a couple of other keywords that can help others to find this post faster: Intel P4 compiler for Tofino (bf-p4c), Tofino Traffic Manager (TM), Tofino Packet Replication Engine (PRE), Tofino Packet Generator (PktGen), Stateful ALU (SALU), Packet Header Vector (PHV), Match-Action Unit (MAU), Ghost Thread, Tofino2, T2NA, Tofino3, T3NA.

Some public information is available here, including a document describing the Tofino Native Architecture (TNA): GitHub - barefootnetworks/Open-Tofino. However, follow-up questions about that repository’s contents should be directed to one of the Intel-specific forums linked above.