It is true that architectures like v1model and TNA have an ingress control and an egress control that you are allowed to fill in with whatever P4 code you want, and then your code will run to process packets at those times (if it compiles successfully, and “fits” into the constraints of the target device, e.g. on total table sizes fitting in the existing memory).
But what are “those times”? In a physical Ethernet switch, there is typically Ethernet MAC hardware that is NOT P4-programmable that first interprets the physical signals received, converts them to a sequence of bits, determines where the beginning and end of the Ethernet frame are, check the CRC, etc. None of that is typically P4-programmable at all, but it is there in the device.
Then ingress parser and ingress code run, as defined by the architecture. Does your P4 ingress code have only access to the packet contents, and nothing else? If the switch has 10 physical ports on it, is your P4 code allowed to know which port the packet arrived on, or not? That is defined by the P4 archticture, and if your P4 code is allowed to know the input port (it is in both v1model and TNA architectures), you can find out what the name of that field is, how many bits in size it is, etc.
Is your P4 ingress code allowed to know a time that the packet arrived? Again, this is defined in the P4 architecture, including what the units of this time value are in for that device, and how many bits wide it is, and thus how frequently it “wraps around” from max value back to 0.
What if you want to drop the packet during ingress processing, and never do egress processing? How can you write P4 code that makes that happen? Again, the P4 architecture defines whether you can do that, or not, and if you can, how you must write code that causes it to happen.
The mechanisms are slightly different between v1model and TNA architectures for all of the things I’ve mentioned. Why? For various detailed implementation reasons of the authors of those architectures.
There is a PNA (Portable NIC architecture) spec in the process of being defined now, and it is quite different from both v1model and TNA in that there is no egress control. Why not? Because NICs are typically designed in hardware quite differently than switch ASICs, is the short answer.