How do registers map to available SRAM?

Hi, I am using an Intel Tofino2-based switch, which says it has ~1.2MB SRAM per stage. I was wondering typically how much of this is available for a P4 register array?

(I am trying to do back-of-the-envelope calculations with this number, sorry I can’t try it myself since I don’t have access to a switch yet).

Thank you!

@mudhaniu – welcome to the forum.

Please, read this post – it will tell you where to get the information

Oh ok I will do that, thank you for your reply!