I use the following code, it rerurns error: Expecting 6 parameters instead of 4 in the 'main' instance
Pipeline(SwitchIngressParser(),
SwitchIngress(),
SwitchIngressDeparser(),
EgressParser1(),
Egress1(),
EgressDeparser1()) pipe;
Switch(pipe) main;
I can’t find out any problems here
There isn’t enough information in this question to diagnose the problem. What compiler are you using and which compile-line flags are you supplying? This code fragment looks good, but perhaps the problem is somewhere else. Perhaps you can show the entire compiled file.
@aoiland – It looks like a fragment of a program written for Tofino or Tofino2. Therefore, you might be better off asking either on ICRP Forum (if you are an academic user) or on Intel Premier Support (if you are commercial user).
But we will ask you to provide the full program too.
Happy hacking,
Vladimir
I used p4c, my code is simple.
#include <core.p4>
#include <tna.p4>
#include "common/util.p4"
#include "common/headers.p4"
struct metadata_t {}
// ---------------------------------------------------------------------------
// Ingress parser
// ---------------------------------------------------------------------------
parser SwitchIngressParser(
packet_in pkt,
out header_t hdr,
out metadata_t ig_md,
out ingress_intrinsic_metadata_t ig_intr_md) {
state start {
pkt.extract(ig_intr_md);
transition select(ig_intr_md.resubmit_flag) {
1 : parse_resubmit;
0 : parse_port_metadata;
}
}
state parse_resubmit {
// Parse resubmitted packet here.
transition reject;
}
state parse_port_metadata {
pkt.advance(64);
transition parse_ethernet;
}
state parse_ethernet {
pkt.extract(hdr.ethernet);
transition accept;
}
}
// ---------------------------------------------------------------------------
// Ingress Deparser
// ---------------------------------------------------------------------------
control SwitchIngressDeparser(
packet_out pkt,
inout header_t hdr,
in metadata_t ig_md,
in ingress_intrinsic_metadata_for_deparser_t ig_dprsr_md) {
apply {
pkt.emit(hdr);
}
}
control SwitchIngress(
inout header_t hdr,
inout metadata_t ig_md,
in ingress_intrinsic_metadata_t ig_intr_md,
in ingress_intrinsic_metadata_from_parser_t ig_prsr_md,
inout ingress_intrinsic_metadata_for_deparser_t ig_dprsr_md,
inout ingress_intrinsic_metadata_for_tm_t ig_tm_md) {
action hit(PortId_t port) {
ig_tm_md.ucast_egress_port = port;
}
action miss() {
ig_dprsr_md.drop_ctl = 0x1; // Drop packet.
}
table forward {
key = {
hdr.ethernet.dst_addr : exact;
}
actions = {
hit;
miss;
}
const default_action = miss;
size = 1024;
}
apply {
forward.apply();
ig_tm_md.bypass_egress = true;
}
}
/**
**/
parser SwitchEgressParser(
packet_in pkt,
out header_t hdr,
out metadata_t eg_md,
out egress_intrinsic_metadata_t eg_intr_md) {
state start{
transition parse_ethernet;
}
state parse_ethernet{
pkt.extract(hdr.ethernet);
transition accept;
}
}
control SwitchEgress(
inout header_t hdr,
inout metadata_t eg_md,
in egress_intrinsic_metadata_t eg_intr_md,
in egress_intrinsic_metadata_from_parser_t eg_intr_md_from_prsr,
inout egress_intrinsic_metadata_for_deparser_t eg_intr_md_for_dprsr,
inout egress_intrinsic_metadata_for_output_port_t eg_intr_md_for_oport){
apply{}
}
control SwitchEgressDeparser(
packet_out pkt,
inout header_t hdr,
in metadata_t eg_md,
in egress_intrinsic_metadata_for_deparser_t ig_intr_dprs_md){
apply{
pkt.emit(hdr.ethernet);
}
}
/**/
Pipeline(SwitchIngressParser(),
SwitchIngress(),
SwitchIngressDeparser(),
SwitchEgressParser(),
SwitchEgress(),
SwitchEgressDeparser()) pipe;
Switch(pipe) main;
I am also considering whether I need to join the Intel academy, but we know the syntax of P4 (we have been studying P4 for a long time), but the hardware environment of TNA is very troublesome. It is convenient to ask whether it costs a lot of money to join the Intel Academy as a research academy？
@aioland,
Thank you for providing the program. However, I want to remind you that while you are allowed to publish your TNA code, you are not allowed to discuss the specifics of SDE and its tools in public (including command-line options, inputs, outputs, error messages, etc.). This gets especially confusing when you are trying to discuss an unofficial preview version of the SDE from 2018 or so(!), which was probably the very first version where P4_16 support even appeared and TNA was still more of a prototype!
The program contains a subtle error (you are including common/util.p4 before you include common/header.p4), and the modern versions of the compiler will give you a much more meaningful message.
With regards to Intel Connectivity Academy and working with Tofino in general. Since you seem to represent an academic institution, you need to know that Intel has a special program, supporting academic and research institutions, called Intel Connectivity Research Program (ICRP). The membership is free and we have members from more than 250 universities and institutions all over the world. The members get access to the latest versions of SDE and they also enjoy generous academic discounts to attend the academy sessions. In fact, we start one tomorrow at 5PM Pacific time.
You can always find Academy schedule on this page, but you need to be an ICRP member to be able to attend the sessions and to see the discounts.
I invite you to join the program and at the same time I would encourage you to refrain posting questions/information on public forums so that you do not accidentally run afool of the NDA.
If you have more question, please write to connectivity.research@intel.com
Happy hacking,
Vladimir
Ok, thank you. We’ll think about it.