Cascading operations in P4

Hii Everyone.

Considering that the target hardware supports multiple inline accelerators like ipsec/tm/frag etc… how can we decide the order of those operations after deparsing is done ? Does the spec defines anything (like egress_metadata or something) that supports this scenario ?


@ShatakshiMishra ,

The order in which individual components are executed (be they P4-programmable or not) is determined by the target’s P4 architecture and can be quite flexible. You need to read the specs for the specific architecture.

Happy hacking,

Thank you @vgurevich