I found that in link_monitor, one of the exercises in tutorials repository, when you are reading from/writing to registers, you use standard_metadata.egress_port as an index. Based on the v1model.p4, I think using standard_metadata.egress_port as index makes no sense!
You can find the problem I referred above here.
I have only skimmed that part of the P4 program you linked very quickly, and not tried to read and understand the entire tutorials exercise it is part of, but it appears to be using a P4 register array, with one element per output port on the switch, where each element is updated so that it is always equal to the total number of bytes of all packets sent to that output port.
Does that match your understanding of what it is trying to do? Can you ask a more specific question about why it does not make any sense?
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Thank you for the clarification. I misunderstood the index. Actually, I did not consider (MAX_PORTS) to make a register as an array of registers!
Every P4 register in the v1model, PSA, and TNA architectures is an array of elements, indexed from 0 up to (size-1).
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