As far as I understand, the Simple_switch implementation of BMV2 uses the V1Model architecture. However, I only found the documentation on the V1Model syntax, but not the details related to the architecture.
I would like to know how many pipelines are supported by V1Model and how many MAU stages are supported by each pipeline?
The BMv2 software switch in the p4lang/behavioral-model repository, which you start with one of the program names simple_switch or simple_switch_grpc, is a software switch. It runs on a general purpose CPU like Intel, AMD, etc. It can execute as large of a P4 program as you are willing to write (up to some extremely large size limits that I have never tried to determine). It does not have MAU stages – it has the hardware of the general purpose CPU that you run it on.
By default, simple_switch and simple_switch_grpc runs multiple threads. One thread runs ingress for all packets. There are 4 threads numbered 0…3 that run egress code for packets destined to different output ports, where packets destined to output port X run on thread (X % 4). Each of these threads on a Linux system typically runs on a separate CPU core, if your system has enough CPU cores available. See the function
start_and_return_ in this file: behavioral-model/simple_switch.cpp at main · p4lang/behavioral-model · GitHub
Multiple threads is similar to running multiple pipelines, in that on a multi-core CPU there are physically separate CPU cores processing packets on different threads.
Thank you so much!
I previously thought that the code in BMV2 and PISA ran in a similar way, with operations in the same stage executed in parallel and operations in different stages executed serially.
I wanted to optimize the logic code so that tables with no dependencies are placed in the same stage as much as possible to speed up the whole pipeline.
Now it seems that I was overthinking and there are still many differences between BVM2’s simple_switch and the real switch. I will check out more technical details in