The concept of P4, programmable data plane, seems very suitable for FPGA platforms. But currently there are only some vendor specific and function-limited P4 to FPGA compilers.
Are there any plans to develop such P4 to FPGA compiler accessible for any vendor/platform?
Is there any group, working on something like PSA/PNA but for FPGA platform, developing architecture description for future P4-programmable FPGA implementations?
A research group of my university is working on parts of what could be a P4 to FPGA compiler. It is not a goal of us to release such a compiler at the moment, but always open to collaborate with the community.
There is the SimpleSumeSwitch architecture from NetFPGA. That could be a starting point for a general P4 architecture that can take advantage of the reconfigurability of FPGA. PNA would also be relevant since FPGA are common in SmartNIC. I believe more than one architecture (or extensions to an architecture) would need to be defined, depending on the goal/purpose of using a FPGA in the network.
One focus of our group is on the microarchitectural implementation of programmable PISA blocks (parser, match-action unit and deparser) for FPGA. Those blocks could be part of a more complete solution, such as what was proposed by P4FPGA, or integrated in a platform like NetFPGA.