“Hi all, I’m working on a layer 2 IPS (PAPDE) and looking at bypassing standard socket APIs for direct DMA access on DPU hardware to ensure wire speed. Does anyone have insights or recent papers on managing PCIe descriptor exhaustion when the P4 data plane is under heavy stateful inspection load? Specifically interested in how this interacts with the Portable Architecture Model (PSA).”
The PSA (Portable Switch Architecture) definition is specifically for switches, with no PCIe typically involved at all, so unlikely to be relevant to your scenario.
The PNA (Portable NIC Architecture) definition is intended for programmable NICs/DPUs. However, it is not fleshed out enough in details on the host interface side enough to address your question, that I can see. Most likely if there is a question of PCIe descriptor exhaustion because the data plane is too busy and getting backed up, those issues would best be answered by the vendor of the specific device you are using.
I was explicitly referring to PNA. What about on a Nvidia Blue field 3 super NIC with arm cores.
Well I don’t think I need address any vendor
I do not know these kinds of details about Nvidia Bluefield 3. I suspect that the only way to find such details is to talk ask Nvidia support. I do not know if Nvidia permits people who know the answers to such questions to discuss them in a public forum, or whether they might require signing an NDA.