Compiling P4 to riscv binary, Can it be realized?

Hi,
I’m learning P4, and I want to support a new architecture (eg VSS, mentioned in P416 Language Specification) on top of P4C, according to README of P4C, I need to implement a new Midend and Backend,
My goal is to generate an executable file, using riscv instructions, that will eventually run on hardware.
My idea is to generate the IR via the P4C backend, then convert the P4 IR to LLVM IR, and finally generate an executable file via the LLVM backend.

I’m not sure if this idea can works? Is there anything to refer to?

  • Extern objects are architecture-specific constructs that can be manipulated by P4 programs through well-defined APIs, but whose internal behavior is hard-wired (e.g., checksum units) and hence not programmable using P4.

If feasible, how should the Extern object and Extern function related to the architecture be implemented? Is it only possible through hardware? Can it be implemented using C/C++?

Thanks,
chiliao

I’m learning P4, and I want to support a new architecture (eg VSS, mentioned in P416 Language Specification) on top of P4C, according to README of P4C, I need to implement a new Midend and Backend,

This implies that you are potentially confusing a P4 architecture definition (VSS, v1model, PSA, PNA, TNA, …) with a CPU architecture (x86, arm, risc-v, …). Do you want to introduce a new P4 architecture (a model of a networking device) or do you want to execute a P4 program (i.e. process network traffic according to a P4 program written for a specific architecture) on a RISC-V CPU?

If it is the former, I am confused by the title of your post, could you clarify? If it is the latter, you do not need to define a new P4 architecture. Depending on what you are trying to do, you may not need to do any change to the p4c compiler either. There are several P4 software switches out there, which “execute” P4 programs. You could try running one of them on RISC-V. For example you could take bmv2 (GitHub - p4lang/behavioral-model: The reference P4 software switch), which is written in C/C++, and try compiling the simple_switch to RISC-V using gcc or clang.

@antonin I’m sorry for not expressing what I mean clearly, what I mean is if I want to design a hardware target (eg a switch device) which supports RISC-V instruction for V1Model architecture. what should I do?

I think I need to do the following:

  1. I need to design a new compiler, but I wonder if I can use P4C directly to convert the IR generated by P4C for the V1Model backend to LLVM IR, and then the LLVM backend generates an executable program consisting of RISCV instructions .
  2. Design hardware devices to implement the V1Model architecture.

I don’t know if my thinking is correct?

Thanks,
chiliao

I am probably not the right person to guide you here. As far as I am concerned, you are still targeting a general purpose platform (RISC-V CPU) and so one of the existing software switches will do just fine, as long as you can compile them (and their dependencies) for RISC-V.

That being said, having a P4C compiler backend that generates LLVM IR could be an interesting research project, I am not sure how practical it is. How do you plan on transforming a P4 match-action table to LLVM IR?
If you look at P4 software switches, they usually take one of 2 approaches:

  • the P4 is transpiled to C or C++ and a compiler toolchain (gcc / clang) is then used to produce an executable (for an arbitrary CPU architecture)
  • the software switch is a “static” program (can be written in any programming language) that interprets the P4 program directly, or rather some configuration file generated by P4C from the P4 program. For example, bmv2 simple_switch is a program written in C/C++ than executes P4 programs by consuming a JSON file generated by P4C from that P4 program

@antonin Thanks for your reply.
I understand that software switches are software, executed as user space processes running on Linux or macOS (or any other operating system on which you can get it to compile and run, but those two operating systems are best supported), on general purposes CPUs such as x86 family CPUs made by Intel and AMD.
but my hardware target has no operating system. so I can not compile the software switch.

  • the P4 is transpiled to C or C++ and a compiler toolchain (gcc / clang) is then used to produce an executable (for an arbitrary CPU architecture)

P4C has supported compile P4 to C, but the target is ebpf, and it needs kernel to load you know. but maybe I can refer to this method.

I see. Thanks for the clarifications, it makes more sense now.
I am a bit out of my depth here, but I think what you are referring to is bare-metal programming for RISC-V processors. It seems that you can do it in C++: RISC-V: A Baremetal Introduction Using C++. Intro. | Medium
That seems like a daunting endeavor in the case of P4 support though. Memory management will be difficult. I don’t know how you plan on doing runtime entry programming (managing match entries in a P4 table).
I hope that there are tools available for bare-metal programming on your target RISC-V system.