# How to arrange multiple registers in one stage?

**URL:** <https://forum.p4.org/t/how-to-arrange-multiple-registers-in-one-stage/1478>\
**Category:** Getting Started with P4\
**Created:** [September 10, 2026, 4:55am UTC](https://forum.p4.org/t/how-to-arrange-multiple-registers-in-one-stage/1478 "2026-09-10T04:55:43Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![LongP4](https://avatars.discourse-cdn.com/v4/letter/l/b38774/32.png) [@LongP4](https://forum.p4.org/u/LongP4)\
**Post date:** [September 10, 2026, 4:55am UTC](https://forum.p4.org/t/how-to-arrange-multiple-registers-in-one-stage/1478/1 "2026-09-10T04:55:44Z")

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I use `@stage` to arrange multiple registers in one stage, but when I arrange more than 4 registers in one stage, I receive a warning, and then the extra registers are arranged into other stages.

 ![2026-09-10 125320](https://us1.discourse-cdn.com/flex019/uploads/p4/original/1X/16f66508c3a76c4c3f2b7930c6762efaf87d679f.png)

However, when I observe through `p4i`, I find that the SRAM Blocks occupied by each register are actually very small, and there are still many SRAM Blocks unused.

How can I arrange more than 4 registers in one stage?

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**Author:** ![andyfingerhut](https://sea1.discourse-cdn.com/flex019/user_avatar/forum.p4.org/andyfingerhut/32/17_2.png) [@andyfingerhut](https://forum.p4.org/u/andyfingerhut)\
**Post date:** [September 10, 2026, 6:15pm UTC](https://forum.p4.org/t/how-to-arrange-multiple-registers-in-one-stage/1478/2 "2026-09-10T18:15:10Z")

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Someone like Vlad could give a more authoritative answer than I can, but if I recall correctly, Tofino hardware may have a designed-in limitation of at most 4 registers in one stage, and that limit is due to other parts of the hardware than how much SRAM those registers use.

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**Author:** ![p4prof](https://sea1.discourse-cdn.com/flex019/user_avatar/forum.p4.org/p4prof/32/251_2.png) [@p4prof](https://forum.p4.org/u/p4prof)\
**Post date:** [September 16, 2026, 5:28am UTC](https://forum.p4.org/t/how-to-arrange-multiple-registers-in-one-stage/1478/3 "2026-09-16T05:28:44Z")

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Dear @LongP4,

@andyfingerhut gave you the right answer.

In your case, the critical resource are the so-called “Meter ALUs”, which are used to implement **all** stateful externs **except** counters (that is meters, registers, low-pass filters (LPFs), weighted random early discard externs (WREDs) and action selector externs). I know, that name migth be a little confusing, but that’s what it is.

The column “S/M ALUs”, located right between the MAP RAMs and the right-hand-side (6x8) group of SRAM blocks represents both the Meter ALUs (M) and the Statistic ALUs (S) – the latter are responsible for the counters. The very top square there is the Meter ALU, the one underneath is a Counter ALU, the one down is the next Meter ALU and so on.

 ![Example: 2 registers using 2 Meter ALUs](https://us1.discourse-cdn.com/flex019/uploads/p4/original/1X/e47136b24d254e0809bda67db1c1d9503d69ebc6.png)

Since this column contains 8 squares, that means that each stage contains 4 meter and 4 counter ALUs. Thus, you can have no more than 4 registers/meters/LPfs/WREDs/ActionSelectors (total) plus 4 counters in any stage.

P4i tool also has a useful “Resource Utilization” section that shows all the resources and their utilization per stage. If some resource is 100% utilized, (in your case you will see that in the stage in question Meter ALU utilization is 100%).

Happy hacking,  
Vladimir