# How do registers map to available SRAM?

**URL:** <https://forum.p4.org/t/how-do-registers-map-to-available-sram/553>\
**Category:** Getting Started with P4\
**Created:** [November 25, 2022, 12:31am UTC](https://forum.p4.org/t/how-do-registers-map-to-available-sram/553 "2022-11-25T00:31:28Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![mudhaniu](https://avatars.discourse-cdn.com/v4/letter/m/e47774/32.png) [@mudhaniu](https://forum.p4.org/u/mudhaniu)\
**Post date:** [November 25, 2022, 12:31am UTC](https://forum.p4.org/t/how-do-registers-map-to-available-sram/553/1 "2022-11-25T00:31:28Z")

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Hi, I am using an Intel Tofino2-based switch, which says it has ~1.2MB SRAM per stage. I was wondering typically how much of this is available for a P4 register array?

(I am trying to do back-of-the-envelope calculations with this number, sorry I can’t try it myself since I don’t have access to a switch yet).

Thank you!

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**Author:** ![vgurevich](https://sea1.discourse-cdn.com/flex019/user_avatar/forum.p4.org/vgurevich/32/23_2.png) [@vgurevich](https://forum.p4.org/u/vgurevich)\
**Post date:** [November 25, 2022, 1:08am UTC](https://forum.p4.org/t/how-do-registers-map-to-available-sram/553/2 "2022-11-25T01:08:14Z")

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@mudhaniu – welcome to the forum.

Please, read [this post](https://forum.p4.org/t/tofino-tna-and-p4studio-questions/504) – it will tell you where to get the information

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**Author:** ![mudhaniu](https://avatars.discourse-cdn.com/v4/letter/m/e47774/32.png) [@mudhaniu](https://forum.p4.org/u/mudhaniu)\
**Post date:** [November 25, 2022, 3:12am UTC](https://forum.p4.org/t/how-do-registers-map-to-available-sram/553/3 "2022-11-25T03:12:09Z")

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Oh ok I will do that, thank you for your reply!