# Future plans on accessible P4 to FPGA toolchain?
**URL:** https://forum.p4.org/t/future-plans-on-accessible-p4-to-fpga-toolchain/60
**Category:** Uncategorized
**Created:** [May 20, 2021, 1:51pm UTC](https://forum.p4.org/t/future-plans-on-accessible-p4-to-fpga-toolchain/60 "2021-05-20T13:51:39Z")
**Posts on this page:** 5
**Page:** 1
### Author:  [@m1a1x1](https://forum.p4.org/u/m1a1x1)
#### Post date: [May 20, 2021, 1:51pm UTC](https://forum.p4.org/t/future-plans-on-accessible-p4-to-fpga-toolchain/60/1 "2021-05-20T13:51:39Z")
The concept of P4, programmable data plane, seems very suitable for FPGA platforms. But currently there are only some vendor specific and function-limited P4 to FPGA compilers.
- Are there any plans to develop such P4 to FPGA compiler accessible for any vendor/platform?
- Is there any group, working on something like PSA/PNA but for FPGA platform, developing architecture description for future P4-programmable FPGA implementations?
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### Author:  [@prst](https://forum.p4.org/u/prst)
#### Post date: [May 25, 2021, 5:21pm UTC](https://forum.p4.org/t/future-plans-on-accessible-p4-to-fpga-toolchain/60/2 "2021-05-25T17:21:34Z")
A research group of my university is working on _parts_ of what could be a P4 to FPGA compiler. It is not a goal of us to release such a compiler at the moment, but always open to collaborate with the community. 🙂
There is the `SimpleSumeSwitch` architecture from NetFPGA. That could be a starting point for a general P4 architecture that can take advantage of the reconfigurability of FPGA. PNA would also be relevant since FPGA are common in SmartNIC. I believe more than one architecture (or extensions to an architecture) would need to be defined, depending on the goal/purpose of using a FPGA in the network.
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### Author:  [@m1a1x1](https://forum.p4.org/u/m1a1x1)
#### Post date: [May 26, 2021, 10:45am UTC](https://forum.p4.org/t/future-plans-on-accessible-p4-to-fpga-toolchain/60/3 "2021-05-26T10:45:13Z")
Is there any publication available, or work is still in early stage? It would be very interesting to look at!
And thank you for the reply!
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### Author:  [@prst](https://forum.p4.org/u/prst)
#### Post date: [May 26, 2021, 1:31pm UTC](https://forum.p4.org/t/future-plans-on-accessible-p4-to-fpga-toolchain/60/4 "2021-05-26T13:31:07Z")
One focus of our group is on the microarchitectural implementation of programmable PISA blocks (parser, match-action unit and deparser) for FPGA. Those blocks could be part of a more complete solution, such as what was proposed by P4FPGA, or integrated in a platform like NetFPGA.
Here is some of our work related to that:
> **[Design Principles for Packet Deparsers on FPGAs](https://arxiv.org/abs/2103.07750)**
>
> The P4 language has drastically changed the networking field as it allows to
> quickly describe and implement new networking applications. Although a large
> variety of applications can be described with the P4 language, current
> programmable switch...
> **[Bridging the Gap: FPGAs as Programmable Switches](https://arxiv.org/abs/2004.07733)**
>
> The emergence of P4, a domain specific language, coupled to PISA, a domain
> specific architecture, is revolutionizing the networking field. P4 allows to
> describe how packets are processed by a programmable data plane, spanning ASICs
> and CPUs,...
> **[P4-compatible High-level Synthesis of Low Latency 100 Gb/s Streaming Packet...](https://arxiv.org/abs/1711.06613)**
>
> Packet parsing is a key step in SDN-aware devices. Packet parsers in SDN
> networks need to be both reconfigurable and fast, to support the evolving
> network protocols and the increasing multi-gigabit data rates. The combination
> of packet processing...
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### Author:  [@m1a1x1](https://forum.p4.org/u/m1a1x1)
#### Post date: [May 26, 2021, 3:27pm UTC](https://forum.p4.org/t/future-plans-on-accessible-p4-to-fpga-toolchain/60/5 "2021-05-26T15:27:02Z")
Great job! Thank you for the links!