# Latest **URL:** https://forum.p4.org/latest.md [Latest](https://forum.p4.org/latest.md) · [Categories](https://forum.p4.org/categories.md) --- ## [Welcome to Discourse](https://forum.p4.org/t/welcome-to-discourse/7)
**Author:** [@system](https://forum.p4.org/u/system)\ **Replies:** 0\ **Last updated:** [April 12, 2021, 9:32pm UTC](https://forum.p4.org/t/welcome-to-discourse/7 "2021-04-12T21:32:43Z")
P4 is just a simple language for declaring how packets are to be processed, yet it turns network system design on its head. With P4, we hope to advance networks from being software-defined to completely programmable, top… --- ## [How to arrange multiple registers in one stage?](https://forum.p4.org/t/how-to-arrange-multiple-registers-in-one-stage/1478)
**Author:** [@LongP4](https://forum.p4.org/u/LongP4)\ **Replies:** 2\ **Last updated:** [September 16, 2026, 5:28am UTC](https://forum.p4.org/t/how-to-arrange-multiple-registers-in-one-stage/1478 "2026-09-16T05:28:44Z")
I use @stage to arrange multiple registers in one stage, but when I arrange more than 4 registers in one stage, I receive a warning, and then the extra registers are arranged into other stages. However, when I observ… --- ## [bf-sde-9.7.0 on Newport (Tofino2) — FPGA not detected on PCIe, platform init fails](https://forum.p4.org/t/bf-sde-9-7-0-on-newport-tofino2-fpga-not-detected-on-pcie-platform-init-fails/1471)
**Author:** [@yiodian.chu](https://forum.p4.org/u/yiodian.chu)\ **Replies:** 0\ **Last updated:** [June 13, 2026, 2:34pm UTC](https://forum.p4.org/t/bf-sde-9-7-0-on-newport-tofino2-fpga-not-detected-on-pcie-platform-init-fails/1471 "2026-06-13T14:34:41Z")
Platform: Intel Newport (Accton AS9516-32D), Tofino2, Ubuntu 20.04, kernel 5.4.0-128 Problem: After installing bf-sde-9.7.0 with newport+asic+tofino2 profile, switchd fails with: BF\_PLTFM ERROR - Error in opening /dev/… --- ## [Packet drops appear after adding src\_tcam\_table.apply() in a Tofino2 P4 pipeline, even when the table is empty](https://forum.p4.org/t/packet-drops-appear-after-adding-src-tcam-table-apply-in-a-tofino2-p4-pipeline-even-when-the-table-is-empty/1464)
**Author:** [@1418915702](https://forum.p4.org/u/1418915702)\ **Replies:** 1\ **Last updated:** [May 12, 2026, 3:46am UTC](https://forum.p4.org/t/packet-drops-appear-after-adding-src-tcam-table-apply-in-a-tofino2-p4-pipeline-even-when-the-table-is-empty/1464 "2026-05-12T03:46:20Z")
Hello everyone, I am implementing a HyperLens-like ACL packet classification pipeline on Intel Tofino2 using P4 and BF-RT. I am testing the forwarding behavior with ClassBench-generated ACL rule sets and packet traces. … --- ## [Need Help Configuring Tofino1 Switch](https://forum.p4.org/t/need-help-configuring-tofino1-switch/1419)
**Author:** [@aaywjaa](https://forum.p4.org/u/aaywjaa)\ **Replies:** 9\ **Last updated:** [May 1, 2026, 3:05pm UTC](https://forum.p4.org/t/need-help-configuring-tofino1-switch/1419 "2026-05-01T15:05:36Z")
We are newcomers to the P4 field. We have a P4 switch with a Tofino1 chip, Debian 11. When deploying the environment according to the vendor’s guide manual, the official document mentions these components and dependent i… --- ## [Optimize Stage Number](https://forum.p4.org/t/optimize-stage-number/1463)
**Author:** [@1418915702](https://forum.p4.org/u/1418915702)\ **Replies:** 6\ **Last updated:** [April 22, 2026, 6:42am UTC](https://forum.p4.org/t/optimize-stage-number/1463 "2026-04-22T06:42:53Z")
Hi all, I have already implemented the basic functionality of a P4 program on Tofino2, including IP lookup and port matching with a TCAM + SRAM bucket/bitmap design, and the program works correctly. My current probl… --- ## [Throughput measurement in Tofino](https://forum.p4.org/t/throughput-measurement-in-tofino/1461)
**Author:** [@1418915702](https://forum.p4.org/u/1418915702)\ **Replies:** 3\ **Last updated:** [April 12, 2026, 2:43am UTC](https://forum.p4.org/t/throughput-measurement-in-tofino/1461 "2026-04-12T02:43:19Z")
Hi, I’m currently working on evaluating the throughput of a Tofino-based switch and have a couple of questions regarding measurement approaches. My topology is shown below. 1. Built-in throughput measurement in Tofi… --- ## [Can Open P4 Studio display memory utilization for table entries, and how can I check it?](https://forum.p4.org/t/can-open-p4-studio-display-memory-utilization-for-table-entries-and-how-can-i-check-it/1459)
**Author:** [@1418915702](https://forum.p4.org/u/1418915702)\ **Replies:** 3\ **Last updated:** [March 26, 2026, 6:07pm UTC](https://forum.p4.org/t/can-open-p4-studio-display-memory-utilization-for-table-entries-and-how-can-i-check-it/1459 "2026-03-26T18:07:16Z")
I’m working with a P4 programmable switch (Intel Tofino-based) and using Open P4 Studio (SDE). I need to monitor the memory usage of my match-action tables, specifically the TCAM and SRAM utilization at the physical memo… --- ## [Unexpected digest batching and delay in BMv2](https://forum.p4.org/t/unexpected-digest-batching-and-delay-in-bmv2/1457)
**Author:** [@Ederroski](https://forum.p4.org/u/Ederroski)\ **Replies:** 2\ **Last updated:** [March 13, 2026, 12:51pm UTC](https://forum.p4.org/t/unexpected-digest-batching-and-delay-in-bmv2/1457 "2026-03-13T12:51:49Z")
I’m testing digest behavior in P4 and I’m seeing results that I don’t quite understand. For testing purposes, the digest is triggered on almost every packet and it is configured with: max\_list\_size = 1 max\_timeout… --- ## [Implementation of priority queues in BMv2](https://forum.p4.org/t/implementation-of-priority-queues-in-bmv2/1455)
**Author:** [@a\_mora](https://forum.p4.org/u/a_mora)\ **Replies:** 7\ **Last updated:** [February 25, 2026, 10:56pm UTC](https://forum.p4.org/t/implementation-of-priority-queues-in-bmv2/1455 "2026-02-25T22:56:06Z")
I enabled the priority queues in simple\_switch\_grpc using the relative command line option --priority-queues \[number of queues\] and I’m queueing packets using the standard metadata priority. I also used the set\_queue\_ra… --- ## [Set up roles for multiple (and remote) controller connections in BMv2](https://forum.p4.org/t/set-up-roles-for-multiple-and-remote-controller-connections-in-bmv2/1454)
**Author:** [@a\_mora](https://forum.p4.org/u/a_mora)\ **Replies:** 12\ **Last updated:** [February 24, 2026, 8:39pm UTC](https://forum.p4.org/t/set-up-roles-for-multiple-and-remote-controller-connections-in-bmv2/1454 "2026-02-24T20:39:02Z")
While reading the P4Runtime API specification, I noticed that a data plane can have multiple controls, even outside the target. The specification states that multiple controllers with write access can be connected to the… --- ## [Xsight XISA and Tofino switches](https://forum.p4.org/t/xsight-xisa-and-tofino-switches/1450)
**Author:** [@trojanezra](https://forum.p4.org/u/trojanezra)\ **Replies:** 4\ **Last updated:** [February 24, 2026, 4:16am UTC](https://forum.p4.org/t/xsight-xisa-and-tofino-switches/1450 "2026-02-24T04:16:49Z")
I noticed that Intel Tofino switches uses P4 but considers the instructions set as a black box. Xsight XISA flagships are the only switches available with documented ISA. I’ve made several adjustments on how we’ll have … --- ## [How to send messages to the control plane from p4 data plane and vice-versa](https://forum.p4.org/t/how-to-send-messages-to-the-control-plane-from-p4-data-plane-and-vice-versa/1452)
**Author:** [@a\_mora](https://forum.p4.org/u/a_mora)\ **Replies:** 1\ **Last updated:** [February 17, 2026, 5:57pm UTC](https://forum.p4.org/t/how-to-send-messages-to-the-control-plane-from-p4-data-plane-and-vice-versa/1452 "2026-02-17T17:57:10Z")
I was trying to find a way to allow control the plane and the data plane to communicate (for example the data plane can notify the control plane when something happens, or the control plane can insert new entries in the … --- ## [DMA access at layer 2 level ](https://forum.p4.org/t/dma-access-at-layer-2-level/1447)
**Author:** [@trojanezra](https://forum.p4.org/u/trojanezra)\ **Replies:** 3\ **Last updated:** [February 17, 2026, 5:48pm UTC](https://forum.p4.org/t/dma-access-at-layer-2-level/1447 "2026-02-17T17:48:37Z")
“Hi all, I’m working on a layer 2 IPS (PAPDE) and looking at bypassing standard socket APIs for direct DMA access on DPU hardware to ensure wire speed. Does anyone have insights or recent papers on managing PCIe descript… --- ## [Advantages of using INT vs. standard Packet-In for attack detection?](https://forum.p4.org/t/advantages-of-using-int-vs-standard-packet-in-for-attack-detection/1431)
**Author:** [@TaikiIto](https://forum.p4.org/u/TaikiIto)\ **Replies:** 2\ **Last updated:** [February 5, 2026, 3:16pm UTC](https://forum.p4.org/t/advantages-of-using-int-vs-standard-packet-in-for-attack-detection/1431 "2026-02-05T15:16:07Z")
Hi everyone, I am currently working on implementing attack detection using P4. In my current implementation, when the switch detects an attack packet in the data plane, it pushes an INT header onto the packet and redire… --- ## [Question about the actual input byte layout for Tofino hash when using multiple fields](https://forum.p4.org/t/question-about-the-actual-input-byte-layout-for-tofino-hash-when-using-multiple-fields/1436)
**Author:** [@LongP4](https://forum.p4.org/u/LongP4)\ **Replies:** 4\ **Last updated:** [February 2, 2026, 2:27pm UTC](https://forum.p4.org/t/question-about-the-actual-input-byte-layout-for-tofino-hash-when-using-multiple-fields/1436 "2026-02-02T14:27:16Z")
Hi, I have a question about the actual input format used by the Tofino hash function when multiple fields are provided as hash inputs. As an example, during packet parsing, I place parsed header contents into the follo… --- ## [Can Tofino2 TCAM support non-contiguous wildcard encoding like 000\*1\*? How to represent it via control plane?](https://forum.p4.org/t/can-tofino2-tcam-support-non-contiguous-wildcard-encoding-like-000-1-how-to-represent-it-via-control-plane/1437)
**Author:** [@1418915702](https://forum.p4.org/u/1418915702)\ **Replies:** 1\ **Last updated:** [February 2, 2026, 3:55am UTC](https://forum.p4.org/t/can-tofino2-tcam-support-non-contiguous-wildcard-encoding-like-000-1-how-to-represent-it-via-control-plane/1437 "2026-02-02T03:55:22Z")
Hi , I have a question about TCAM matching capability on Tofino2, especially regarding non-contiguous wildcard patterns. Suppose I want to install a TCAM entry with the following bit-level match pattern: LCP = 000\*1\* … --- ## [Are registers in BMv2 initialized to zero?](https://forum.p4.org/t/are-registers-in-bmv2-initialized-to-zero/1434)
**Author:** [@a\_mora](https://forum.p4.org/u/a_mora)\ **Replies:** 2\ **Last updated:** [January 30, 2026, 7:43pm UTC](https://forum.p4.org/t/are-registers-in-bmv2-initialized-to-zero/1434 "2026-01-30T19:43:14Z")
Hi everyone, I was wondering if registers are guaranteed to be initialized to 0 when using BMv2 (specifically simple\_switch\_grpc) and, if so, whether this is also common on other targets. I looked through the P4 langua… --- ## [DPDK and P4C version requirements](https://forum.p4.org/t/dpdk-and-p4c-version-requirements/1432)
**Author:** [@dd2111843](https://forum.p4.org/u/dd2111843)\ **Replies:** 1\ **Last updated:** [January 27, 2026, 7:55pm UTC](https://forum.p4.org/t/dpdk-and-p4c-version-requirements/1432 "2026-01-27T19:55:24Z")
Hello, I’m currently conducting real-device testing, but I’ve encountered some issues. We installed p4c but the DPDK couldn’t be run. --- ## [Why the counter does not work as expect?](https://forum.p4.org/t/why-the-counter-does-not-work-as-expect/1425)
**Author:** [@herano1999](https://forum.p4.org/u/herano1999)\ **Replies:** 5\ **Last updated:** [January 14, 2026, 9:23am UTC](https://forum.p4.org/t/why-the-counter-does-not-work-as-expect/1425 "2026-01-14T09:23:19Z")
I wrote a Tofino P4 program, and I can successfully compile it with open-p4studio. #include \ #if \_\_TARGET\_TOFINO\_\_ == 3 #include \ #elif \_\_TARGET\_TOFINO\_\_ == 2 #include \ #else #include \ … --- ## [Sanity check: MMF-based controller for BMv2/Mininet with host-side policing](https://forum.p4.org/t/sanity-check-mmf-based-controller-for-bmv2-mininet-with-host-side-policing/1412)
**Author:** [@kacperkuczynski26](https://forum.p4.org/u/kacperkuczynski26)\ **Replies:** 4\ **Last updated:** [December 14, 2025, 10:00pm UTC](https://forum.p4.org/t/sanity-check-mmf-based-controller-for-bmv2-mininet-with-host-side-policing/1412 "2025-12-14T22:00:31Z")
Hi all, I’m prototyping a small P4Runtime controller that tries to enforce network-wide max–min fairness (progressive filling) over a 6-switch mesh in Mininet/BMv2. I’d really appreciate a sanity check: does this archit… --- ## [P4 GSoC 2026 Mentor Recruitment](https://forum.p4.org/t/p4-gsoc-2026-mentor-recruitment/1413)
**Author:** [@Dscano](https://forum.p4.org/u/Dscano)\ **Replies:** 0\ **Last updated:** [December 10, 2025, 7:30pm UTC](https://forum.p4.org/t/p4-gsoc-2026-mentor-recruitment/1413 "2025-12-10T19:30:56Z")
Hello everyone, P4 org is planning to participate in Google Summer of Code (GSoC) again this year. An important part of our application is identifying mentors from the community, so we’re reaching out to find volunteer … --- ## [How to implementing ARP in BMv2 Switch](https://forum.p4.org/t/how-to-implementing-arp-in-bmv2-switch/1411)
**Author:** [@TaikiIto](https://forum.p4.org/u/TaikiIto)\ **Replies:** 7\ **Last updated:** [December 8, 2025, 7:39am UTC](https://forum.p4.org/t/how-to-implementing-arp-in-bmv2-switch/1411 "2025-12-08T07:39:33Z")
Hello,All. I would like to implement custom ARP processing using P4 on a BMv2 switch. My goal is to implement the following logic: ARP Requests: When the switch receives an ARP packet, it should broadcast (flood) it to… --- ## [BMv2 port congestion packet drops analysis using egress\_spec counters shared buffer queue behavior](https://forum.p4.org/t/bmv2-port-congestion-packet-drops-analysis-using-egress-spec-counters-shared-buffer-queue-behavior/1410)
**Author:** [@cjb20001108](https://forum.p4.org/u/cjb20001108)\ **Replies:** 4\ **Last updated:** [December 1, 2025, 5:11pm UTC](https://forum.p4.org/t/bmv2-port-congestion-packet-drops-analysis-using-egress-spec-counters-shared-buffer-queue-behavior/1410 "2025-12-01T17:11:47Z")
If only one specific output port becomes the bottleneck link in BMv2 due to high outgoing traffic, is it valid to measure that port’s packet loss by maintaining two counters: (1) a counter in the ingress pipeline that c… --- ## [\[P4Runtime/BMv2\] Packets dropped despite inserting TableEntry via Python controller](https://forum.p4.org/t/p4runtime-bmv2-packets-dropped-despite-inserting-tableentry-via-python-controller/1408)
**Author:** [@kacperkuczynski26](https://forum.p4.org/u/kacperkuczynski26)\ **Replies:** 3\ **Last updated:** [November 26, 2025, 12:00am UTC](https://forum.p4.org/t/p4runtime-bmv2-packets-dropped-despite-inserting-tableentry-via-python-controller/1408 "2025-11-26T00:00:02Z")
Hello everyone, I am working on a project using Mininet, BMv2 (simple\_switch\_grpc), and P4Runtime. My goal is to migrate from static table configuration (using s1-runtime.json files loaded at startup) to a dynamic Pytho… --- ## [P4/Tofino: Best practices for fallback metaifno matching (primary → secondary) without duplicate apply or heavy memory usage?](https://forum.p4.org/t/p4-tofino-best-practices-for-fallback-metaifno-matching-primary-secondary-without-duplicate-apply-or-heavy-memory-usage/1409)
**Author:** [@1418915702](https://forum.p4.org/u/1418915702)\ **Replies:** 3\ **Last updated:** [November 25, 2025, 6:59pm UTC](https://forum.p4.org/t/p4-tofino-best-practices-for-fallback-metaifno-matching-primary-secondary-without-duplicate-apply-or-heavy-memory-usage/1409 "2025-11-25T18:59:57Z")
Hi， I’m implementing a 3-stage packet classification on Tofino: Stage-1: IP/Proto TCAM → outputs two metaifno (primary, secondary). Stage-2: SRC port matching — use metaifno to lookup either TCAM or SRAM. Requiremen… --- ## [Clone to CPU: First packet received by the controller, other not received](https://forum.p4.org/t/clone-to-cpu-first-packet-received-by-the-controller-other-not-received/1407)
**Author:** [@louis.barbier41](https://forum.p4.org/u/louis.barbier41)\ **Replies:** 1\ **Last updated:** [November 24, 2025, 12:56pm UTC](https://forum.p4.org/t/clone-to-cpu-first-packet-received-by-the-controller-other-not-received/1407 "2025-11-24T12:56:22Z")
Hello everyone, I’m currently debugging an issue with the PacketIn mechanism in my P4Runtime controller (Python, asyncio). I implemented the same architecture as the flow-cache example: a processNotif task, an asyncio Q… --- ## [Help with bmv2/v1model meter + “color” usage for Max–Min Fairness (P4 Tutorial VM)](https://forum.p4.org/t/help-with-bmv2-v1model-meter-color-usage-for-max-min-fairness-p4-tutorial-vm/1402)
**Author:** [@kacperkuczynski26](https://forum.p4.org/u/kacperkuczynski26)\ **Replies:** 2\ **Last updated:** [November 24, 2025, 12:03am UTC](https://forum.p4.org/t/help-with-bmv2-v1model-meter-color-usage-for-max-min-fairness-p4-tutorial-vm/1402 "2025-11-24T00:03:44Z")
Hi all, I’m using the recommended “P4 Tutorial Development” VM (prebuilt from the official P4 repo). I’m trying to modify basic.p4 to prototype a max–min fairness (MMF) controller: the controller computes per-flow rates… --- ## [Integrate STF with p4testgen](https://forum.p4.org/t/integrate-stf-with-p4testgen/1406)
**Author:** [@gzrccfy](https://forum.p4.org/u/gzrccfy)\ **Replies:** 3\ **Last updated:** [November 23, 2025, 6:26pm UTC](https://forum.p4.org/t/integrate-stf-with-p4testgen/1406 "2025-11-23T18:26:22Z")
I’m trying to use p4testgen to generate test case for my p4-16 program. p4testgen --target bmv2 --arch v1model --test-backend STF --out-dir tests --max-tests 5 basic\_forwarding.p4 And I’m trying to use the python scrip… --- ## [Does P4 Support a Popcount Operation on Any Target?](https://forum.p4.org/t/does-p4-support-a-popcount-operation-on-any-target/1405)
**Author:** [@1418915702](https://forum.p4.org/u/1418915702)\ **Replies:** 1\ **Last updated:** [November 18, 2025, 7:41am UTC](https://forum.p4.org/t/does-p4-support-a-popcount-operation-on-any-target/1405 "2025-11-18T07:41:30Z")
Hi， I would like to confirm whether P4 (P4\_16) support a popcount / bit-count operation in the data plane. If not, then implementing popcount manually in P4 seems like it would consume many pipeline stages — is that re… [Next page](https://forum.p4.org/latest.md?page=1)